Spirent Communications has announced a collaboration with Cadence Design Systems, to deliver a joint networking system-on-chip (SoC) verification solution that bridges the gap between pre-silicon and post-silicon verification. 

The collaboration brings sophisticated virtual Ethernet traffic emulation and testing capabilities to pre-silicon verification in the Cadence Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems. Highly scalable and flexible, the solution has the capacity to emulate any port speed from 1G to 800G at the application level, and quickly introduce additional features to enable new use cases as required.

Jointly developed, the solution is designed to enable the increasing data bandwidths needed to verify designs for data centres and other high-performance applications. The partnership combines the data rates and port densities of Spirent TestCenter, with verification capabilities of the Cadence Palladium and Protium systems as a unified solution with reusable, portable, automated test cases.

Unique benefits of the joint solution include:

  • Effective, efficient testing for pre-silicon validation from 1G to 800G for application-level testing
  • Comprehensive integration of the test application and emulation environment without the need for external test hardware
  • Cost savings from identifying and fixing issues in early-stage chip design
  • A unified test platform that bridges gaps between pre- and post-silicon verification, enabling continuity of testing from the earliest phases of product development through customer deployment
  • Capability to test all phases of silicon product lifecycle, time-saving application re-utilisation, implementation of standard metrics for more effective measurement and result analysis, and easy integration into CI/CD workflows,
  • Acceleration of the entire silicon development lifecycle

Download the Spirent Chip Design Verification Solution datasheet.

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